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ZL30122 SONET/SDH Low Jitter Line Card Synchronizer
Data Sheet
May 2006
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Ordering Information ZL30122GGG 64 Pin CABGA Trays ZL30122GGG2 64 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC * Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz Provides 3 sync inputs for output frame pulse alignment Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency Configurable input to output delay, and output to output phase alignment Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities Supports IEEE 1149.1 JTAG Boundary Scan
Features
* Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 Internal APLL provides standard output clock frequencies up to 622.08 MHz with jitter < 3 ps RMS suitable for GR-253-CORE OC-12 and G.813 STM-16 interfaces Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz Digital Phase Locked-Loop (DPLL) provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth
*
* * * *
*
*
*
trst_b tck tdi tms
tdo
dpll_lock
dpll_holdover
diff_en
osco osci
Master Clock
IEEE 1449.1 JTAG
ref0 ref1 ref2
ref2:0
ref
diff_clk_p/n SONET/SDH APLL sdh_clk sdh_fp p_clk p_fp
DPLL
sync0 sync1 sync2 sync2:0 Reference Monitors ref_&_sync_status
sync
Programmable Synthesizer
int_b
SPI Interface
Controller & State Machine
sck
si
so
cs_b
rst_b
dpll_mod_sel
sdh_filter
filter_ref0
filter_ref1
Figure 1 - Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30122
Applications
* * * * * * AMCs for AdvancedTCATM and MicroTCA Systems Multi-Service Edge Switches or Routers DSLAM Line Cards WAN Line Cards RNC/Mobile Switching Center Line Cards ADM Line Cards
Data Sheet
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ZL30122 Table of Contents
Data Sheet
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 DPLL Mode Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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ZL30122 List of Figures
Data Sheet
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Automatic Mode State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3 - Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6 - Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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ZL30122 List of Tables
Data Sheet
Table 1 - DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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ZL30122
Pin Description Pin # Name I/O Type Description
Data Sheet
Input Reference B1 A3 B4 A1 A2 A4 ref0 ref1 ref2 sync0 sync1 sync2 Id Input References (LVCMOS, Schmitt Trigger). These are input references available for synchronizing output clocks. All three input references can be automatically or manually selected using software registers. These pins are internally pulled down to Vss. Frame Pulse Synchronization References (LVCMOS, Schmitt Trigger). These are the frame pulse synchronization inputs associated with input references 0, 1 and 2. These inputs accept frame pulses in a clock format (50% duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns. These pins are internally pulled down to Vss. SONET/SDH Output Clock (LVCMOS). This output can be configured to provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default frequency for this output is 77.76 MHz. SONET/SDH Output Frame Pulse (LVCMOS). This output can be configured to provide virtually any style of output frame pulse synchronized with an associated SONET/SDH family output clock. The default frequency for this frame pulse output is 8 kHz. Programmable Output Clock (LVCMOS). This output can be configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz. The default frequency for this output is 2.048 MHz. Programmable Output Frame Pulse (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with p_clk. The default frequency for this frame pulse output is 8 kHz. Differential Output Clock (LVPECL). This output can be configured to provide any one of the available SDH clock frequencies. The default frequency for this clock output is 622.08 MHz.
Id
Output Clocks and Frame Pulses D8 sdh_clk O
D7
sdh_fp
O
G8
p_clk
O
G7
p_fp
O
A7 B8 Control G5
diff_clk_p diff_clk_n
O
rst_b
I
Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To ensure proper operation, the device must be reset after power-up. Reset should be asserted for a minimum of 300 ns. DPLL Mode Select (LVCMOS, Schmitt Trigger). During reset, the level on this pin determines the default mode of operation of the DPLL (Normal or Freerun). After reset, the mode of operation can be controlled directly with these pins, or by accessing the dpll_modesel register through the serial interface. This pin is internally pulled up to Vdd. Differential Output Enable (LVCMOS, Schmitt Trigger). When set high, the differential LVPECL driver is enabled. When set low, the differential driver is tristated reducing power consumption. This function is also controllable through software registers. This pin is internally pulled up to Vdd.
B2
dpll_mod_sel
Iu
B3
diff_en
Iu
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ZL30122
Pin # Status E1 dpll_lock O Name I/O Type Description
Data Sheet
Lock Indicator (LVCMOS). This is the lock indicator pin for the DPLL. This output goes high when the DPLL's output is frequency and phase locked to the input reference. Holdover Indicator (LVCMOS). This pin goes high when the DPLL enters the holdover mode.
H1
dpll_holdover
O
Serial Interface C1 D2 D1 C2 E2 sck si so cs_b int_b I I O Iu O Clock for Serial Interface (LVCMOS). Serial interface clock. Serial Interface Input (LVCMOS). Serial interface data input pin. Serial Interface Output (LVCMOS). Serial interface data output pin. Chip Select for Serial Interface (LVCMOS). Serial interface chip select. This pin is internally pulled up to Vdd. Interrupt Pin (LVCMOS). Indicates a change of device status prompting the processor to read the enabled interrupt service registers (ISR). This pin is an open drain, active low and requires an external pulled up to VDD.
APLL Loop Filter A5 B5 C5 sdh_filter filter_ref0 filter_ref1 A A A External Analog PLL Loop Filter terminal. Analog PLL External Loop Filter Reference. Analog PLL External Loop Filter Reference.
JTAG and Test G4 tdo O Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of tck. This pin is held in high impedance state when JTAG scan is not enabled. Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it should be left unconnected. Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on powerup to ensure that the device is in the normal functional state. This pin is internally pulled up to Vdd. If this pin is not used then it should be connected to GND. Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND. Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected.
G2
tdi
Iu
G3
trst_b
Iu
H3 F2
tck tms
I Iu
Master Clock H4 osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz reference from a clock oscillator (XO, XTAL). The stability and accuracy of the clock at this input determines the free-run accuracy and the long term holdover stability of the output clocks.
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ZL30122
Pin # H5 Name osco I/O Type O Description
Data Sheet
Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected when the osci pin is connected to a clock oscillator.
Miscellaneous F5 H6 H7 H2 IC IC NC IC Internal Connection. Leave unconnected. Internal Connection. Connect to ground. No Connection. Leave unconnected. Internal Connection. Connect to ground.
Power and Ground C3 C8 E8 F6 F8 G6 H8 E6 F3 B7 C4 B6 C7 F1 D3 D4 D5 D6 E3 E4 E5 E7 F4 F7 A6 A8 C6 G1
IId Iu OAPG-
VDD
P P P P P P P P P P P P P P G G G G G G G G G G G G G G
Positive Supply Voltage. +3.3VDC nominal.
VCORE AVDD AVCORE
Positive Supply Voltage. +1.8VDC nominal. Positive Analog Supply Voltage. +3.3VDC nominal. Positive Analog Supply Voltage. +1.8VDC nominal.
VSS
Ground. 0 Volts.
AVSS
Analog Ground. 0 Volts.
Input Input, Internally pulled down Input, Internally pulled up Output Analog Power Ground
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ZL30122
1.0 Functional Description
Data Sheet
The ZL30122 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. The DPLL is capable of locking to one of three input references and provides a wide variety of synchronized output clocks and frame pulses.
1.1
DPLL Features
The Digital Phase-Locked Loop synchronizes to one of the qualified references and provides automatic or manual hitless reference switching and a holdover function when no qualified references are available. It provides a highly configurable set of features which are configurable through the serial interface. A summary of these features are shown in Table 1. Feature Modes of Operation Loop Bandwidth Phase Slope Limiting Pull-in Range Reference Inputs Sync Inputs Input Reference Frequencies Supported Sync Input Frequencies Input Reference Selection/Switching Hitless Reference Switching Output Clocks Output Frame Pulses Supported Output Clock Frequencies Supported Output Frame Pulse Frequencies External Pins Status Indicators Free-run, Normal (locked), Holdover User selectable: 14 Hz, 28 Hz, or wideband1 (890 Hz / 56 Hz / 14 Hz) User selectable: 885 ns/s, 7.5 s/s, 61 s/s, or unlimited Fixed: 130 ppm Ref0, Ref1, Ref2 Sync0, Sync1, Sync2 2 kHz, N * 8 kHz up to 77.76 MHz 166.67 Hz, 400 Hz, 1 kHz, 2 kHz, 8 kHz, 64 kHz. Automatic (based on programmable priority and revertiveness), or manual selection Can be enabled or disabled diff_p/n, sdh_clk, p_clk sdh_fp, p_fp synchronized to active sync reference. As listed in Table 4 As listed in Table 4 Lock, Holdover Table 1 - DPLL Features
1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or greater than 64 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to or greater than 8 kHz and less than 64 kHz, the loop bandwidth = 56 Hz. For reference frequencies equal to 2 kHz, the loop bandwidth is equal to 14 Hz.
DPLL
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ZL30122
1.2 DPLL Mode Of Operation
Data Sheet
The DPLL supports three modes of operation - free-run, normal, and holdover. The mode of operation can be manually set or controlled by an automatic state machine as shown in Figure 2.
All references are monitored for frequency accuracy and phase regularity, and at least one reference is qualified.
Reset
Free-Run
Another reference is qualified and available for selection
Lock Acquisition
No references are qualified and available for selection
Holdover
Phase lock on the selected reference is achieved
Selected reference fails
Normal Normal (Locked) (Locked)
Figure 2 - Automatic Mode State Machine Free-run The free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to a reference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the external master oscillator. Lock Acquisition The input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given a stable reference input, the ZL30122 will enter in the Normal (locked) mode. Normal (locked) The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency accuracy of the reference input. While in the normal mode, the DPLL's clock and frame pulse outputs comply with the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication standards. Holdover When the DPLL operating in the normal mode loses its reference input, and no other qualified references are available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data collected while the DPLL was synchronized. The transition between normal and holdover modes is controlled by the DPLL so that its initial frequency offset is better than 100 ppb. The frequency drift after this transition period is dependant on the frequency drift of the external master oscillator.
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ZL30122
1.3 Ref and Sync Inputs
Data Sheet
There are three reference clock inputs (ref0 to ref2) available to the DPLL. Reference selection can be controlled using a built-in state machine or set in a manual mode.The selected reference input is used to synchronize the output clocks.
ref2:0
DPLL sync2:0
Figure 3 - Reference and Sync Inputs In addition to the reference inputs, the DPLL has three optional frame pulse synchronization inputs (sync0 to sync2) used to align the output frame pulses. The syncn input is selected with its corresponding refn input, where n = 0, 1, or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of the frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4.
n = 0, 1, 2 Without a frame pulse signal at the sync input, the output frame pulses will align to any arbitrary cycle of its associated output clock.
refn syncn - no frame pulse signal present
diff_clk/sdh_clk/p_clk sdh/p_fp
When a frame pulse signal is present at the sync input, the DPLL will align the output frame pulses to the output clock edge that is aligned to the input frame pulse.
n = 0, 1, 2
refn syncn
diff_clk/sdh_clk/p_clk sdh_fp/p_fp
Figure 4 - Output Frame Pulse Alignment
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ZL30122
Data Sheet
Each of the ref inputs accept a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz. Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8 kHz are also available. 2 kHz 8 kHz 64 kHz 1.544 MHz 2.048 MHz 6.48 MHz 8.192 MHz 16.384 MHz 19.44 MHz 38.88 MHz 77.76 MHz Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies Each of the sync inputs accept a single-ended LVCMOS frame pulse. Since alignment is determined from the rising edge of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width requirement of 5 ns. Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies shown in Table 3. 166.67 Hz (48x 125 s frames) 400 Hz 1 kHz 2 kHz 8 kHz 64 kHz Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies
1.4
Ref and Sync Monitoring
All input references (ref0 to ref2) are monitored for frequency accuracy and phase regularity. New references are qualified before they can be selected as a synchronization source, and qualified references are continuously monitored to ensure that they are suitable for synchronization. The process of qualifying a reference depends on four levels of monitoring. Single Cycle Monitor (SCM) The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure (scm_fail) is declared.
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ZL30122
Coarse Frequency Monitor (CFM)
Data Sheet
The CFM block monitors the reference frequency over a measurement period of 30 s so that it can quickly detect large changes in frequency. A CFM failure (cfm_fail) is triggered when the frequency has changed by more than 3% or approximately 30000 ppm. Precise Frequency Monitor (PFM) The PFM block measures the frequency accuracy of the reference over a 10 second interval. To ensure an accurate frequency measurement, the PFM measurement interval is re-initiated if phase or frequency irregularities are detected by the SCM or CFM. The PFM provides a level of hysteresis between the acceptance range and the rejection range to prevent a failure indication from toggling between valid and invalid for references that are on the edge of the acceptance range. When determining the frequency accuracy of the reference input, the PFM uses the external oscillator's output frequency (focsi) as its point of reference. Guard Soak Timer (GST) The GST block mimics the operation of an analog integrator by accumulating failure events from the CFM and the SCM blocks and applying a selectable rate of decay when no failures are detected. As shown in Figure 5, a GST failure (gst_fail) is triggered when the accumulated failures have reached the upper threshold during the disqualification observation window. When there are no CFM or SCM failures, the accumulator decrements until it reaches its lower threshold during the qualification window. CFM or SCM failures ref
upper threshold
lower threshold td gst_fail tq
td - disqualification time tq - qualification time = n * td
Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures Sync Ratio Monitor All sync inputs (sync0 to sync2) are continuously monitored to ensure that there is a correct number of reference clock cycles within the frame pulse period.
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ZL30122
1.5 Output Clocks and Frame Pulses
Data Sheet
The ZL30122 offers a wide variety of outputs including one low-jitter differential LVPECL clock (diff_clk_p/n), one SONET/SDH LVCMOS (sdh_clk) output clock and one programmable LVCMOS (p_clk) output clock. In addition to the clock outputs, one LVCMOS SONET/SDH frame pulse output (sdh_fp) and one LVCMOS programmable frame pulse (p_fp) is also available.
Programmable Synthesizer DPLL SONET/SDH APLL
p_clk p_fp
diff_clk_p/n
sdh_clk sdh_fp
Figure 6 - Output Configuration The supported frequencies for the output clocks and frame pulses are shown in Table 4. diff_clk_p/n (LVPECL) 6.48 MHz 19.44 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz 311.04 MHz 622.08 MHz sdh_clk (LVCMOS) 6.48 MHz 9.72 MHz 12.96 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz Table 4 - Output Clock and Frame Pulse Frequencies p_clk (LVCMOS) 2 kHz N * 8 kHz (up to 77.76 MHz) sdh_fp, p_fp (LVCMOS) 166.67 Hz (48x 125 s frames) 400 Hz 1 kHz 2 kHz 4 kHz 8 kHz 32 kHz 64 kHz
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ZL30122
1.6 Configurable Input-to-Output and Output-to-Output Delays
Data Sheet
The ZL30122 allows programmable static delay compensation for controlling input-to-output and output-to-output delays of its clocks and frame pulses. Both the SONET/SDH APLL and the Programmable Synthesizer can be configured to lead or lag the selected input reference clock using the DPLL Fine Delay. The delay is programmed in steps of 119.2 ps with a range of -128 to +127 steps giving a total delay adjustment in the range of -15.26 ns to +15.14 ns. Negative values delay the output clock, positive values advance the output clock. In addition to the delay introduced by the DPLL Fine Delay, the SONET/SDH APLL and programmable synthesizer have the ability to add their own fine delay adjustments using the P Fine Delay and SDH Fine Delay. These delays are also programmable in steps of 119.2 ps with a range of -128 to +127 steps. In addition to these delays, the single-ended output clocks of the SONET/SDH and Programmable synthesizers can be independently offset by 90, 180 and 270 degrees using the Coarse Delay, and the SONET/SDH differential outputs can be independently delayed by -1.6 ns, 0 ns, +1.6 ns or +3.2 ns using the Diff Delay. The output frame pulses (sdh_clk, p_fp) can be independently offset with respect to each other using the FP Delay.
Diff Delay DPLL SDH Fine Delay SONET/SDH APLL Coarse Delay FP Delay
diff_clk_p/n sdh_clk sdh_fp
P Fine Delay
Programmable Synthesizer
Coarse Delay FP Delay
p_clk p_fp
DPLL Fine Delay
Feedback Synthesizer
Figure 7 - Phase Delay Adjustments
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ZL30122
2.0 Software Configuration
Data Sheet
The ZL30122 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The device can be configured to operate in a highly automated manner which minimizes its interaction with the system's processor, or it can operate in a manual mode where the system processor controls most of the operation of the device. The following table provides a summary of the registers available for status updates and configuration of the device.
.
Addr (Hex)
Register Name
Reset Value (Hex)
Description
Type
Miscellaneous Registers 00 01 id_reg use_hw_ctrl A6 00 Chip and version identification and reset ready indication register Allows some functions of the device to be controlled by hardware pins Interrupts 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ref_fail_isr dpll_isr Reserved ref_mon_fail_0 ref_mon_fail_1 Reserved Reserved ref_fail_isr_mask dpll_isr_mask Reserved ref_mon_fail_mask_0 ref_mon_fail_mask_1 Reserved Reserved FF FF 00 00 FF FF FF 70 Reference failure interrupt service register DPLL interrupt service register Leave as default Ref0 and ref1 failure indications Ref2 failure indication. Leave as default Leave as default Reference failure interrupt service register mask DPLL interrupt service register mask Leave as default Control register to mask each failure indicator for ref0 and ref1 Control register to mask failure indicator for ref2 Leave as default Leave as default Reference Monitor Setup 10 11 12 13 detected_ref_0 detected_ref_1 Reserved Reserved FF FF Ref0 and ref1 auto-detected frequency value status register Ref2 auto-detected frequency value status register Leave as default Leave as default Table 5 - Register Map R R R R R/W R/W R/W R/W StickR StickR R StickR R R/W
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Addr (Hex) 14 15 16 17 18 19 1A 1B 1C Register Name detected_sync_0 detected_sync_1 oor_ctrl_0 oor_ctrl_1 Reserved Reserved gst_mask Reserved gst_qualif_time 1A FF Reset Value (Hex) EE 0E 33 33
Data Sheet
Description Sync0 and sync1 auto-detected frequency value and sync failure status register Sync2 auto-detected frequency value and sync valid status register Control register for the ref0 and ref1 out of range limit Control register for the ref2 out of range limit Leave as default Leave as default Control register to mask the inputs to the guard soak timer for ref0 - ref2 Leave as default Control register for the guard_soak_timer qualification time and disqualification time for the references DPLL Control
Type R R R/W R/W
R/W
R/W
1D
dpll_ctrl_0
See Register Description See Register Description See Register Description 00 3C
Control register for the DPLL filter control; phase slope limit, bandwidth and hitless switching Holdover update time, filter_out_en, freq_offset_en, revert enable Control register for the DPLL mode of operation DPLL reference selection or reference selection status Control register to mask each failure indicator (SCM, CFM, PFM and GST) used for automatic reference switching and automatic holdover Control register to indicate the time to restore a previous failed reference Control register for the ref0 to ref2 enable revertive signals Control register for the ref0 and ref1 priority values Control register for the ref2 priority values Leave as default Leave as default
R/W
1E
dpll_ctrl_1
R/W
1F
dpll_modesel
R/W
20 21
dpll_refsel dpll_ref_fail_mask
R/W R/W
22 23 24 25 26 27
dpll_wait_to_restore dpll_ref_rev_ctrl dpll_ref_pri_ctrl_0 dpll_ref_pri_ctrl_1 Reserved Reserved
00 00 10 32
R/W R/W R/W R/W
Table 5 - Register Map (continued)
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Addr (Hex) 28 29 2A 35 Register Name dpll_lock_holdover_status Reserved Reserved Reset Value (Hex) 04 03 Leave as default Leave as default Programmable Synthesizer Configuration Registers 36 37 38 39 3A 3B 3C 3D p_enable p_run p_freq_0 p_freq_1 p_clk_offset90 Reserved Reserved p_offset_fine 00 8F 0F 00 01 00 Control register to enable the p_clk and p_fp outputs of the programmable synthesizer Control register to generate p_clk, p_fp Control register for the [7:0] bits of the N of N*8k clk Control register for the [13:8] bits of the N of N*8k clk Control register for the p_clk phase position coarse tuning Leave as default Leave as default Control register for the output/output phase alignment fine tuning for the programmable synthesizer
Data Sheet
Description DPLL lock and holdover status register
Type R R/W
R/W R/W R/W R/W R/W
R/W
3E 3F 40 41 42 43 4F
p_fp_freq p_fp_type p_fp_fine_offset_0 p_fp_fine_offset_1 p_fp_coarse_offset Reserved
05 83 00 00 00
Control register to select the p_fp frame pulse frequency Control register to select p_fp type Bits [7:0] of the programmable frame pulse phase offset in multiples of 1/262.14 MHz Bits [15:8] of the programmable frame pulse phase offset in multiples of 1/262.14 MHz Programmable frame pulse phase offset in multiples of 8 kHz cycles Leave as default
R/W R/W R/W R/W R/W
SDH Configuration Registers 50 51 52 53 sdh_enable sdh_run sdh_clk_div sdh_clk_offset90 8F 0F 42 00 Control register to enable sdh_clk and sdh_fp Control register to generate sdh_clk and sdh_fp Control register for the sdh_clk frequency selection Control register for the sdh_clk phase position coarse tuning R/W R/W R/W R/W
Table 5 - Register Map (continued)
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Zarlink Semiconductor Inc.
ZL30122
Addr (Hex) 54 55 56 57 58 59 5A 5B 5F Register Name Reserved sdh_offset_fine sdh_fp_freq sdh_fp_type sdh_fp_fine_offset_0 sdh_fp_fine_offset_1 sdh_fp_coarse_offset Reserved 00 05 23 00 00 00 Reset Value (Hex) Leave as default Control register for the output/output phase alignrment fine tuning for sdh path Control register to select the sdh_fp frame pulse frequency Control register to select sdh_fp type Bits [7:0] of the programmable frame pulse phase offset in multiples of 1/311.04 MHz Bits [15:8] of the programmable frame pulse phase offset in multiples of 1/311.04 MHz Programmable frame pulse phase offset in multiples of 8 kHz cycles Leave as default Differential Output Configuration 60 61 diff_clk_ctrl diff_clk_sel A3 53 Control register to enable diff_clk
Data Sheet
Description
Type
R/W R/W R/W R/W R/W R/W
R/W R/W
Control register to select the diff_clk frequency
External Feedback Configuration 62 63 64 65 66 67 Reserved fb_offset_fine reserved Custom Input Frequencies ref_freq_mode_0 Reserved custA_mult_0 00 00 Control register to set whether to use auto detect, CustomA or CustomB for ref0 to ref2 Leave as default Control register for the [7:0] bits of the custom configuration A. This is the N integer for the N*8kHz reference monitoring. Control register for the [13:8] bits of the custom configuration A. This is the N integer for the N*8kHz reference monitoring. Control register for the custom configuration A: single cycle SCM low limiter Control register for the custom configuration A: single cycle SCM high limiter Control register for the custom configuration A: The [7:0] bits of the single cycle CFM low limit R/W R/W F5 Leave as default Control register for the output/output phase alignment fine tuning R/W
68
custA_mult_1
00
R/W
69 6A 6B
custA_scm_low custA_scm_high custA_cfm_low_0
00 00 00
R/W R/W R/W
Table 5 - Register Map (continued)
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Zarlink Semiconductor Inc.
ZL30122
Addr (Hex) 6C Register Name custA_cfm_low_1 Reset Value (Hex) 00
Data Sheet
Description Control register for the custom configuration A: The [15:0] bits of the single cycle CFM low limit Control register for the custom configuration A: The [7:0] bits of the single cycle CFM high limit Control register for the custom configuration A: The [15:0] bits of the single cycle CFM high limiter Control register for the custom configuration A: CFM reference monitoring cycles - 1 Control register for the custom configuration A: enable the use of ref_div4 for the CFM and PFM inputs Control register for the [7:0] bits of the custom configuration B. This is the 8 k integer for the N*8kHz reference monitoring. Control register for the [13:8] bits of the custom configuration B. This is the 8 k integer for the N*8kHz reference monitoring. Control register for the custom configuration B: single cycle SCM low limiter Control register for the custom configuration B: single cycle SCM high limiter Control register for the custom configuration B: The [7:0] bits of the single cycle CFM low limiter. Control register for the custom configuration B: The [15:0] bits of the single cycle CFM low limiter. Control register for the custom configuration B: The [7:0] bits of the single cycle CFM high limiter. Control register for the custom configuration B: The [15:0] bits of the single cycle CFM high limiter. Control register for the custom configuration B: CFM reference monitoring cycles - 1 Control register for the custom configuration B: enable the use of ref_div4 for the CFM and PFM inputs
Type R/W
6D
custA_cfm_hi_0
00
R/W
6E
custA_cfm_hi_1
00
R/W
6F 70
custA_cfm_cycle custA_div
00 00
R/W R/W
71
custB_mult_0
00
R/W
72
custB_mult_1
00
R/W
73 74 75
custB_scm_low custB_scm_high custB_cfm_low_0
00 00 00
R/W R/W R/W
76
custB_cfm_low_1
00
R/W
77
custB_cfm_hi_0
00
R/W
78
custB_cfm_hi_1
00
R/W
79 7A
custB_cfm_cycle custB_div
00 00
R/W R/W
Table 5 - Register Map (continued)
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Zarlink Semiconductor Inc.
ZL30122
Addr (Hex) 7B 7F Register Name Reserved Table 5 - Register Map (continued) Reset Value (Hex)
Data Sheet
Description
Type
3.0
References
AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group.
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Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2005 All rights reserved.
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